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IRQCFG0D bits
7..6
7..6
3
5..4
2
Cfg
00, 1X
01
X
XX
X
State
RX
RX
TX
RX
TX
IRQ
0
0
0
1
1
Source
Start Pattern Detect
RSSI
no signal (0)
DCLK
DCLK
Table 77
The motivation for disabling clocking when transmitting or receiving OOK is that non-standard bit rates can be
used. However, the host microcontroller must handle the data and clock recovery functions. When using continu-
ous mode with or without clocking enabled, data should be encoded to provide DC-balance (same number of 1
and 0 bits) and limited run lengths of the same bit value. Manchester encoding, 8-to-12 bit symbolizing or scram-
bling must be applied to the data before transmitting and removed after receiving to achieve good RF transmis-
sion performance. The preamble, start pattern and error checking bits must also be generated by the host micro-
controller to establish robust data communications.
6.6.2 Buffered Data Mode
In Buffered data mode operation, the transmitted and received data bits pass through the SPI port in groups of
8 bits to the internal TRC105 FIFO. Bits flow from the FIFO to the modulator for transmission and are loaded into
the FIFO as data is received. As discussed in Sections 3.10 and 3.11, the SPI port can address the data FIFO or
the configuration registers. Asserting a logic low on the nSS_DATA input addresses the FIFO, and asserting a
logic low on the nSS_CONFIG addresses the configuration registers. If both of these inputs are asserted,
nSS_CONFIG will override nSS_DATA. The TRC105 acts as an SPI slave and receives clocking from its host
microcontroller. SPI read/write details are provided in Sections 3.10 and 3.11. As shown in Figure 19, two inter-
rupt (control) outputs, IRQ0 and IRQ1, are provided by the TRC105 to coordinate SPI data flow to and from the
host microcontroller. One to four signals can be selected or mapped to each interrupt output. This mapping is con-
figured in register IRQCFG0D . Bits 7..6 select the signal for IRQ0 in the receive mode, and Bit 3 selects the IRQ0
signal in transmit mode. Bits 5..4 select the signal for IRQ1 in the receive mode, and Bit 2 selects the IRQ1 signal
in transmit mode. The mapping options for Buffered data mode are summarized in Table 78:
IRQCFG0D bits
7..6
7..6
7..6
7..6
3
3
5..4
5..4
5..4
5..4
2
2
Cfg
00
01
10
11
1
0
00
01
10
11
0
1
State
RX
RX
RX
RX
TX
TX
RX
RX
RX
RX
TX
TX
IRQ
0
0
0
0
0
0
1
1
1
1
1
1
Source
no signal (0)
Write_byte (high pulse when received byte written to FIFO)
nFIFOEMPTY
Start Pattern Detect
FIFO_Int_Tx
nFIFOEMPTY
no signal (0)
FIFOFULL
RSSI_IRQ
FIFO_Int_Rx
FIFOFULL
TX_Stop
Table 78
www.RFM.com E-mail: info@rfm.com
? 2009-2013 by RF Monolithics, Inc.
Technical support +1.800.704.6079
Page 57 of 67
TRC105 - 05/29/13
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